, Research Paper
Digital Block Design
The Digital Block is the heart of this digitally controlled function generator. Symmetry and frequency variation is direct result of the design of this block. In this design the emphasis was on simplicity and some target specifications at the top of the frequency variation were compromised in order to achieve greater simplicity. This design achieves 28 frequencies in the range of 100Hz to 100kHz. Whilst the 17 frequencies from the range 100Hz to 10kHz are symmetry variable in five steps from 0.1 to 0.5. The last eight frequencies only managed to achieve symmetry variations 0.5 and 0.25. This is due to some limiting factors that will be discussed later. The table of achievable frequencies can be found at the end of this report.
User inputs are also digitally processed in this function generator and sent out as digital signals to other parts of this function generator namely the amplifier module. Also a filter selector circuit is built in after the digital block. The user inputs controlling frequency and symmetry are also built into this control block.
Therefore it is clear that the digital block can be divided into 4 distinct blocks, each with its own functionality. These blocks are the control module, counter module, filter control module and 8-bit D/A. The D/A chosen is the DAC0801LCN. It s specifications can be found in the appendix. The layout of this design is shown below.
The interconnections will be discussed later but the thickness of the lines indicates the number of bits in the bus lines.
As the name suggests the control module takes user inputs, processes them and sends them out to the respective modules. The functionality module generates the count, varying between 0 to 255 in 256 steps or in 64 steps. The 8-bit D/A changes this count into a wave and the filter selector module selects which filter in the filter block to pass the signal through.
While extensive testing has been done on the functionality module, the control module and filter selector module are relatively simple and have not been tested due to the inability to do so. The control module consists primarily of switches and ROM s while the filter selection module is made up of two analogue multiplexers. These modules are discussed in further detail in later sections.
This block essentially converts user input into digital signals. We have four user inputs coming in, and five control signals outputted, with the extra output being generated internally. This function is carried out as follows:
There are two basic types of inputs: One being a graduated circular switch, and the other a simple up/down switch. Their basic function is outlined below:
Up/down switch: This is basically a toggle switch which can be switched from VCC to Ground [Logic 1 or 0].
Circular Graduated switch: This is a switch much like the controls on most scopes. Switch rotation moves a contact along a potentiometer. This contact is connected to an A/D converter. The number of bits of the A/D converter is different for each input.
The four user inputs are as follows:
Type: This utilizes the up/down device. Up (Logic 1) corresponds to a Triangle wave and Down (Logic 0) corresponds to a Square wave. This signal is fed simultaneously to the digital and Filter block. A Logic 0 (Square) will cause the filter to be bypassed as the square wave does not require filtering.
Symmetry: This employs the circular switch. 8 different symmetries are provided. Consequently, a 3-bit ADC is used. The provided symmetries and their binary is as follows:
000: 8/16 | 001: 9/16 | 010: 10/16 | 011: 11/16 | 100: 12/16 | 101: 13/16 | 110: 14/16 | 111: 15/16 |
Amplitude: This also utilizes the circular switch. This control signal is fed straight through to a multiplexer in the amplifier block. We are providing 16 different amplitudes. Therefore, a 4-bit ADC is used. The amplitudes and their corresponding binary is as follows:
0000: 10mV |0001: 20mV |0010: 40mV |0011: 60mV |
0100: 80mV |0101: 0.1V |0110: 0.2V |0111: 0.4V |
1000: 0.6V |1001: 0.8V |1010: 1.0V |1011: 2.0V |
1100: 4.0V |1101: 6.0V |1110: 8.0V |1111: 10.0V |
Frequency: 28 different values of frequency are provided using a 5-bit ADC in the circular switch. These are fed into a 5 input multiplexer which selects the frequency from the clock divider block. The frequencies are as follows:
00000: 100Hz | 00001: 200Hz |00010: 300Hz | 00011: 400Hz | 00100: 500Hz |
00101: 600Hz | 00110: 700Hz |00111: 800Hz | 01000: 900Hz | 01001: 1000Hz |
01010: 2000Hz |01011: 3000Hz |01100: 4000Hz |01101: 5000Hz | 01110: 6000Hz |
01111: 7000Hz |10000: 8000Hz |10001: 9000Hz |10010: 10000Hz|10011: 20000Hz |
10100: 30000Hz |10101: 40000Hz|10110: 50000Hz | 10111: 60000Hz|11000: 70000Hz|
11001: 80000Hz |11010: 90000Hz|11011: 100000Hz|
Band/Frequency selector: This is the internally generated output mentioned above. It selects which filter is used corresponding to the frequency band the chosen user frequency is in. This generated by passing the 5-bit frequency value to a multiplexer which then send a 4-bit binary number to another multiplexer in the filter block (We have 10 bands ). The bands and there values are as follows:(All in kHz)
0000: 0.1 | 0001: 0.2-0.3 | 0010: 0.4-0.6 | 0011: 0.7-1.0 | 0100: 2.0-3.0 |
0101: 4.0-6.0 | 0110: 7.0-10.0 | 0111: 20.0-30.0 | 1000: 40.0-60.0 | 1001: 70.0-100.0|
As mentioned before, this module is the heart of the whole function generator as this is the module that generates the signal in the form of a binary number which is passed through the 8-bit D/A. Therefore this was obviously the first design problem to be tackled.
Whilst the details of the design itself has gone through many revisions the concept behind the design is still the same. A clock pulse generator generates a signal which is then passed through MOD-N counters to divide the frequency and then fed into an 8-bit counter which generated the wave by counting from 0 to 255 and back down. However we shall see that this is an oversimplification of the problem. However before we look at the design we shall firstly look at the problems associated with this design and the target specifications.
Most problems in sequential circuits arise from timing considerations and this project is of no exception. Firstly it must be taken into account that most of the circuit will be designed with the use of flip-flops.
First before we elaborate on the timing considerations of the flip-flops we should look at the task we have. To produce a 100kHz triangle wave which consists of 256 steps up and 256 steps down would require a input clock signal of at least 51.2Mhz. Coming back to flip-flops, the fmax, which is the maximum clock frequency for the flip-flop to trigger reliably is typically 50Mhz. Therefore this makes the approach of feeding a clock through MOD-N counters and then into an 8-bit counter impossible unless the symmetry variation for the top frequency range was ignored.
This finite value of fmax raises further problems as we seek a way to approach the problems of varying the symmetry and frequency. Because the frequency can only be divided by integers, if we fed a clock signal which was just capable of providing a 100kHz wave the next frequency achieved would be 50kHz. Obviously this is not desirable. Also obvious is the approach to overcoming this problem is to feed a signal that has a higher frequency than is required. However this again brings into consideration of the value of fmax.
Also to do with frequency variation it is impractical to vary the frequency bye just one discrete range from 100Hz to 100kHz. Therefore the approach of having course and fine steps, where course is the decade steps. Therefore the frequency variation are not variable in linear steps but only in linear steps in the log domain.
Varying the symmetry can also be approached in two ways. Either we can vary the step height, i.e. the counter counts irregularly. Or we could also vary the step width, i.e. the counter takes longer to count up one step. Both have clear advantages and disadvantages. Varying the step height will make frequency accuracy extremely difficult besides making the counter design more complicated. Varying the step width would make the required input clock frequency higher again. This approach allows us to keep the frequency more accurate.
Fixed Clock Speed
Before we move on to our choice of clock speed we first describe how the functionality module actually works. We have set a target maximum input clock frequency of not more than 55Mhz and therefore had to work around this. Firstly a decision to compromise the design specifications at the top end of the frequency range (above 10kHz) in order to simplify the design. However this was found to be insufficient as we still could not vary frequency or symmetry properly. Therefore the decision was taken to make the count at the upper range (above 10kHz) smaller, i.e. a 6-bit count. This would enable us to vary symmetry in 5 steps from t/T of 0.1 to 0.5 for the range 100Hz to 10kHz and keep the frequency steps the same throughout the entire range.
In the table below are the key difficulties and the compromises made.
Key Problems Choices Choice of solution
1. The finite value of fmax raised problems with the varying of symmetry and frequency at the top range. · Compromise the frequency variation at the top end.
· Compromise the symmetry variation at the top end.
· Alter the counter design to include different step heights. · Compromised symmetry variation as frequency variation is viewed as more important
· Alter counter to count to 255 in only 64 steps.
2. How to approach the frequency variation · Multiple different MOD counters varying frequency for the whole range.
· Staggered variable MOD counters to vary frequency by sub ranges, in this case decades. · Staggered MOD counters as it saves chips and also divides the whole range so that no ridiculous MOD numbers are required.
3. How to approach the symmetry variation. · Varying the step height. This approach would complicate the counter design.
· Vary the up and down step heights, this would complicate the circuitry driving the counter.
· Vary the up and down clock, fortunately there is a standard chip that does this. · The easiest approach was taken and that was to vary the up down clock cycles. This means that additional MOD counters are used to vary the up and down clocks to achieve symmetry variation. (74193)
In order to achieve full symmetry variation the clock speed has to be 10 times the required input clock signal for a 10kHz wave, this is therefore 25.5Mhz. However to vary the frequency more decently it is decided that the input clock should be doubled therefore the final input clock frequency is 51Mhz.
At the top decade however, while the frequency variation was not compromised, the symmetry had to be cut down from 5 steps to 2 steps due to the clock speed limitations. A further description of this module is in the following pages.
This module can be divided into three different modules, firstly the frequency division module, then the symmetry variation module and lastly the counter module. Here we will go into detail how each module works, starting with the counter, as the rest of the design is built around it.
This module is built around the 74193 counter. This IC has two clock inputs for the up count and the down count. This allows easy variation of the waveform symmetry as the up count and the down count can have different clock speeds. The truth table is given below.
Clr Up Dn Q3 Q2 Q1 Q0 CON BON
0 Clock 1 Count Up H H
0 1 Clock Count Down H H
0 Clock 1 1 1 1 1 L H
0 1 Clock 0 0 0 0 H L
The 74193 is a 4-bit counter therefore we need to cascade it with another counter in order to make it a 8-bit counter. Tying CON output to the Up input of the second 74193 and the BON output to the Dn input does this. Also some logic is required to hold Dn high when the counter is counting up and Up high when counter is counting down.
This is done with the use of an OR gate. The two clock inputs are fed into two different OR gates and so the count can be held high by logic on the other input of the gates. These inputs have been given the node names CLK_UP and CLK_DN. The logic is generated by a sequential circuit based around a JK flip-flop. As it can be seen from the circuit layout, when all outputs of the counter are high , i.e. the count is 255, the output of the AND gate is high thus setting the JK flip-flop. When all outputs are low, i.e. the count is 0 then the NOR gate resets the flip-flop. The output and the inverted output are fed into the OR gate s controlling the Up and Dn inputs of the counter respectively. This design also allows the count number to be varied between 0 to 255 and this is done to implement a 6-bit counter for the top frequency decade. The multiplexers simply chose whether the counter is counting from 0 to 255 or 0 to 127.
To generate a square wave, the count must equal 255 when the counter is counting up and equal 0 when the counter is counting down. This looks suspiciously like the CLK_DN output of the multiplexers. This output is fed into the line2bus which simply feeds one input into 8 outputs, thus generating the 0 to 255 variation.
While the 6-bit counter counts from 0 to 127, the 8-bit D/A requires that we count from 0 to 255 for a proper signal to be generated. This is done by the 8bit26bit. The 6LSB of the count are simply fed into the 6MSB of the output while the 2LSB outputs are kept at 1. The 8bit21mux simply selects whether the signal outputted to the D/A is a square signal or a triangle signal. Finally the 8-bit sampler is simply 8 D-flip-flops which are driven with the same clock pulse in order to facilitate the synchronization of the output bits.
All in all this module is very self contained and only requires two inputs, up clock and down clock. Both of which are generated by the symmetry variation module.
Symmetry Variation Module
The function of this module is simply to take an input clock signal and split it and divide the two by different MOD numbers. However the selection of these numbers is critical to the achieved symmetry as well as the frequency accuracy. Therefore we shall now look again at the target specifications.
For a waveform with a symmetry of t/T=0.1, the down clock must be 9 times as fast as the up clock.