--DS1851.vhd
--Data Separator for AD1851/AD1861/AD1862/AD1865 parallel DAC
library ieee ;
use ieee.std_logic_1164.all ;
entity DS1851 is
port (
RST : in std_logic;
SCLK : in std_logic;
SDATA : in std_logic;
LRCLK : in std_logic;
RL1 : in std_logic;
RL0 : in std_logic;
LE : out std_logic;
CLK : out std_logic;
DOL : out std_logic;
DOR : out std_logic
);
end DS1851;
architecture v1 of DS1851 is
component SPREG16R
port ( RST : in std_logic ;
CLK : in std_logic ;
SI : in std_logic ;
Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8 : out std_logic ;
Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 : out std_logic
) ;
end component ;
component SPREG32R
port ( RST : in std_logic ;
CLK : in std_logic ;
SI : in std_logic ;
Q31,Q30,Q29,Q28,Q27,Q26,Q25,Q24 : out std_logic;
Q23,Q22,Q21,Q20,Q19,Q18,Q17,Q16 : out std_logic;
Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8 : out std_logic ;
Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 : out std_logic
) ;
end component ;
component DFFR
port (RST : in std_logic ;
CLK : in std_logic ;
D : in std_logic ;
Q : out std_logic ;
QN : out std_logic
) ;
end component ;
component INV
port (
IN0 : in std_logic ;
Z : out std_logic
) ;
end component;
component BUF
port (
IN0 : in std_logic ;
Z : out std_logic
) ;
end component ;
component MUX41
port (IN0,IN1,IN2,IN3,SEL0,SEL1 : in std_logic ;
Z : out std_logic
) ;
end component ;
signal nLRCLK, pLRCLK, nSCLK, pSCLK, nSDATA, pSDATA : std_logic;
signal i24b, i20b, i18b, i16b : std_logic;
signal RESET, iDOL, iDOR, iCLK, iLE : std_logic;
begin
RSTI: INV port map (IN0 => RST, Z => RESET);
DD1A: INV port map (IN0 => SCLK, Z => nSCLK);
DD1D: INV port map (IN0=> nSCLK, Z => pSCLK);
DD1B: INV port map (IN0 => SDATA, Z => nSDATA);
DD1E: INV port map (IN0 => nSDATA, Z => pSDATA);
DD1C: INV port map (IN0 => LRCLK, Z => nLRCLK);
DD1F: INV port map (IN0 => nLRCLK, Z => pLRCLK);
CLKB: BUF port map (IN0 => nSCLK, Z => iCLK);
DD2: SPREG16R port map (RST => RESET, CLK => pSCLK, SI => pSDATA,
Q7 => i24b, Q11 => i20b, Q13 => i18b, Q15 => i16b);
DDMX: MUX41 port map (IN0 => i24b, IN1 => i20b, IN2 => i18b, IN3 => i16b,
SEL0 => RL0, SEL1 => RL1, Z => iDOR);
DD4: DFFR port map (RST => RESET, D => pLRCLK, CLK => pSCLK, Q => iLE);
DD5: SPREG32R port map (RST => RESET, CLK => pSCLK, SI => iDOR,
Q31 => iDOL);
BUFE: BUF port map (IN0 => iLE, Z => LE);
BUFC: BUF port map (IN0 => iCLK, Z => CLK);
BUFL: BUF port map (IN0 => iDOL, Z => DOL);
BUFR: BUF port map (IN0 => iDOR, Z => DOR);
end v1 ;
--DS1853.vhd
--Data Separator for AD1852/AD1853 delta-sigma DAC
library ieee ;
use ieee.std_logic_1164.all ;
entity DS1853 is
port (
RST : in std_logic;
BCLK : in std_logic;
SDATA : in std_logic;
LRCLK : in std_logic;
MCLK : in std_logic;
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_L : out std_logic;
SDATA_R : out std_logic;
MCLK_O : out std_logic
);
end DS1853;
architecture v1 of DS1853 is
component SPREG64R
port ( RST : in std_logic ;
CLK : in std_logic ;
SI : in std_logic ;
Q63,Q62,Q61,Q60,Q59,Q58,Q57,Q56 : out std_logic;
Q55,Q54,Q53,Q52,Q51,Q50,Q49,Q48 : out std_logic;
Q47,Q46,Q45,Q44,Q43,Q42,Q41,Q40 : out std_logic;
Q39,Q38,Q37,Q36,Q35,Q34,Q33,Q32 : out std_logic;
Q31,Q30,Q29,Q28,Q27,Q26,Q25,Q24 : out std_logic;
Q23,Q22,Q21,Q20,Q19,Q18,Q17,Q16 : out std_logic;
Q15,Q14,Q13,Q12,Q11,Q10,Q9,Q8 : out std_logic;
Q7,Q6,Q5,Q4,Q3,Q2,Q1,Q0 : out std_logic
) ;
end component ;
component DFFR
port (RST : in std_logic ;
CLK : in std_logic ;
D : in std_logic ;
Q : out std_logic ;
QN : out std_logic
) ;
end component ;
component INV
port (
IN0 : in std_logic ;
Z : out std_logic
) ;
end component;
component BUF
port (
IN0 : in std_logic ;
Z : out std_logic
) ;
end component ;
component MUX21
port (IN0,IN1,SEL : in std_logic ;
Z : out std_logic
) ;
end component ;
signal iBCLK, iSDATA, iLRCLK, iMCLK : std_logic;
signal RESET, nLRCLK, pLRCLK : std_logic;
signal o31, o63, o31n, o31p, o63n, bSDATA: std_logic;
begin
INBB: BUF port map (IN0 => BCLK, Z => iBCLK);
INBS: BUF port map (IN0 => SDATA, Z => bSDATA);
INBL: BUF port map (IN0 => LRCLK, Z => iLRCLK);
INBM: BUF port map (IN0 => MCLK, Z => iMCLK);
RSTI: INV port map (IN0 => RST, Z => RESET);
DD12A: DFFR port map (RST => RESET, D => iLRCLK,
CLK => iBCLK, Q => pLRCLK, QN => nLRCLK);
DD12B: DFFR port map (RST => RESET, D => bSDATA,
CLK => iBCLK, Q => iSDATA);
DD1: SPREG64R port map (RST => RESET, SI => iSDATA,
CLK => iBCLK, Q31 => o31, Q63 => o63);
O31B: BUF port map (IN0 => o31, Z => o31p);
O31I: INV port map (IN0 => o31, Z => o31n);
O63I: INV port map (IN0 => o63, Z => o63n);
MUXL: MUX21 port map (IN0 => o63n, IN1 => o31p,
SEL => pLRCLK, Z => SDATA_L);
MUXR: MUX21 port map (IN0 => o31n, IN1 => iSDATA,
SEL => pLRCLK, Z => SDATA_R);
INVL: INV port map (IN0 => pLRCLK, Z => LRCLK_O);
INVB: INV port map (IN0 => iBCLK, Z => BCLK_O);
INVM: INV port map (IN0 => iMCLK, Z => MCLK_O);
end v1 ;
Далее необходимо составить код для генератора отладочной последовательности.
--Tester1851.vhd
--Test signal generator for DS1851
library ieee ;
use ieee.std_logic_1164.all ;
entity Tester1851 is
port (
CLK : in std_logic
);
end Tester1851;
architecture v1 of Tester1851 is
component TS1851
port (
RST : out std_logic;
SCLK : in std_logic;
SDATA : out std_logic;
LRCLK : out std_logic
);
end component ;
component DS1851
port (
RST : in std_logic;
SCLK : in std_logic;
SDATA : in std_logic;
LRCLK : in std_logic;
RL1 : in std_logic;
RL0 : in std_logic;
LE : out std_logic;
CLK : out std_logic;
DOL : out std_logic;
DOR : out std_logic
);
end component ;
component BUF
port (
IN0 : in std_logic ;
Z : out std_logic
) ;
end component ;
signal SCLK, SDATA, LRCLK, RST : std_logic;
signal LD1, LD2, LD3, RD1, RD2, RD3, DSReg : std_logic_vector (31 downto 0);
begin
D0: BUF port map (IN0 => CLK, Z => SCLK);
D2: DS1851 port map (RST => RST, SCLK => SCLK,
SDATA => SDATA, LRCLK => LRCLK,
RL1 => '1', RL0 => '1');
Test: process
begin
LD1 <= "01100110000000011000000000000000";
RD1 <= "01111000000001111000000000000000";
LD2 <= "01100110000111111000000000000000";
RD2 <= "01111000011111111000000000000000";
LD3 <= "01100111111111111000000000000000";
RD3 <= "01111111111111111000000000000000";
SDATA <= '0';
LRCLK <= '1';
RST <= '0';
wait for 50ns;
RST <= '1';
wait on SCLK until SCLK='0';
DSReg <= LD1;
wait for 10ns;
LRCLK <= '0';
SDATA <= DSReg(31);
LD1L: for i in 30 downto 0 loop
wait on SCLK until SCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop LD1L;
wait on SCLK until SCLK='0';
DSReg <= RD1;
wait for 10ns;
LRCLK <= '1';
SDATA <= DSReg(31);
RD1L: for i in 30 downto 0 loop
wait on SCLK until SCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop RD1L;
wait on SCLK until SCLK='0';
DSReg <= LD2;
wait for 10ns;
LRCLK <= '0';
SDATA <= DSReg(31);
LD2L: for i in 30 downto 0 loop
wait on SCLK until SCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop LD2L;
wait on SCLK until SCLK='0';
DSReg <= RD2;
wait for 10ns;
LRCLK <= '1';
SDATA <= DSReg(31);
RD2L: for i in 30 downto 0 loop
wait on SCLK until SCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop RD2L;
wait on SCLK until SCLK='0';
DSReg <= LD3;
wait for 10ns;
LRCLK <= '0';
SDATA <= DSReg(31);
LD3L: for i in 30 downto 0 loop
wait on SCLK until SCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop LD3L;
wait on SCLK until SCLK='0';
DSReg <= RD3;
wait for 10ns;
LRCLK <= '1';
SDATA <= DSReg(31);
RD3L: for i in 30 downto 0 loop
wait on SCLK until SCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop RD3L;
wait on SCLK until SCLK='0';
DSReg <= LD1;
wait for 10ns;
LRCLK <= '0';
wait;
end process;
end v1;
--Tester1853.vhd
--Test signal generator for DS1853
library ieee ;
use ieee.std_logic_1164.all ;
entity Tester1853 is
port (
CLK : in std_logic
);
end Tester1853;
architecture v1 of Tester1853 is
component TS1853
port (
RST : out std_logic;
SCLK : in std_logic;
SDATA : out std_logic;
LRCLK : out std_logic
);
end component ;
component DS1853
port (
RST : in std_logic;
BCLK : in std_logic;
SDATA : in std_logic;
LRCLK : in std_logic;
MCLK : in std_logic;
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_L : out std_logic;
SDATA_R : out std_logic;
MCLK_O : out std_logic
);
end component ;
component BUF
port (
IN0 : in std_logic ;
Z : out std_logic
) ;
end component ;
signal BCLK, SDATA, LRCLK, RST : std_logic;
signal LD1, LD2, LD3, RD1, RD2, RD3, DSReg : std_logic_vector (31 downto 0);
begin
D0: BUF port map (IN0 => CLK, Z => BCLK);
D2: DS1853 port map (RST => RST, BCLK => BCLK,
SDATA => SDATA, LRCLK => LRCLK,
MCLK => BCLK);
Test: process
begin
LD1 <= "01100110000000011000000000000000";
RD1 <= "01111000000001111000000000000000";
LD2 <= "01100110000111111000000000000000";
RD2 <= "01111000011111111000000000000000";
LD3 <= "01100111111111111000000000000000";
RD3 <= "01111111111111111000000000000000";
SDATA <= '0';
LRCLK <= '1';
RST <= '0';
wait for 50ns;
RST <= '1';
wait on BCLK until BCLK='0';
DSReg <= LD1;
wait for 10ns;
LRCLK <= '0';
SDATA <= DSReg(31);
LD1L: for i in 30 downto 0 loop
wait on BCLK until BCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop LD1L;
wait on BCLK until BCLK='0';
DSReg <= RD1;
wait for 10ns;
LRCLK <= '1';
SDATA <= DSReg(31);
RD1L: for i in 30 downto 0 loop
wait on BCLK until BCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop RD1L;
wait on BCLK until BCLK='0';
DSReg <= LD2;
wait for 10ns;
LRCLK <= '0';
SDATA <= DSReg(31);
LD2L: for i in 30 downto 0 loop
wait on BCLK until BCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop LD2L;
wait on BCLK until BCLK='0';
DSReg <= RD2;
wait for 10ns;
LRCLK <= '1';
SDATA <= DSReg(31);
RD2L: for i in 30 downto 0 loop
wait on BCLK until BCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop RD2L;
wait on BCLK until BCLK='0';
DSReg <= LD3;
wait for 10ns;
LRCLK <= '0';
SDATA <= DSReg(31);
LD3L: for i in 30 downto 0 loop
wait on BCLK until BCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop LD3L;
wait on BCLK until BCLK='0';
DSReg <= RD3;
wait for 10ns;
LRCLK <= '1';
SDATA <= DSReg(31);
RD3L: for i in 30 downto 0 loop
wait on BCLK until BCLK='0';
DSReg <= DSReg(30 downto 0) & '0';
wait for 10ns;
SDATA <= DSReg(31);
end loop RD3L;
wait on BCLK until BCLK='0';
DSReg <= LD1;
wait for 10ns;
LRCLK <= '0';
wait;
end process;
endv1;
При выполнении работы были рассмотрены вопросы реализации разделения цифрового потока от приемника сигнала SPDIF (и/или AES/EBU) для подачи его непосредственно на микросхемы ЦАП. Из набора наиболее часто используемых способов реализации были выбраны наиболее универсальные и лучшим образом отвечающие требованиям стандарта.
При схемной реализации была выполнена оптимизация схемы для получения наилучших условий прохождения сигнала. Также была затронута проблема обеспечения качественной фильтрации питания в аппаратуре с большим числом цифровых микросхем.
В результате выполнения работы были получены работающие схемы, пригодные к воплощению в готовом устройстве. Работа схем была промоделирована на языке VHDL. Помимо VHDL моделей был получен готовый код, пригодный для прошивки кристалла ПЛМ.
Тем не менее, основным результатом работы следует считать закрепление знаний по дисциплинам "Прикладная теория цифровых автоматов", "Цифровая схемотехника" и "Моделирование на языке VHDL", а также повышение опыта работы с соответствующими средствами и способами разработки.