# Mentor Graphics Essay Research Paper ObjectiveTo complete

СОДЕРЖАНИЕ: Mentor Graphics Essay, Research Paper Objective To complete all aspects of the exercise regarding D type flip-flop, TTL and CMOS and to familiarize us with the HDL software which is Mentor Graphics. This software is capable of constructing and simulating a particular design.

Mentor Graphics Essay, Research Paper

Objective

To complete all aspects of the exercise regarding D type flip-flop, TTL and CMOS and to familiarize us with the HDL software which is Mentor Graphics. This software is capable of constructing and simulating a particular design.

As for this assignment 1, we are given 4 weeks to complete the assignment. It is compulsory to attend every lab sessions as there is no alternative software to use. Only a certain limit of time is given for the use of the software and therefore designing of circuit is required to be completed before attending the lab. To give students a first-hand understanding of the EDA lab and most importantly Mentor Graphics, a powerful tool in HDL technology.

This assignment allows the students to understand or rather familiarize themselves with the design flow of the EDA software and to fully explore what the software is capable and powerful to do.

Lastly, to prepare the students for the next assignments which uses the similar software.

Introduction – D(elay) Flip-Flop (What You Have to Know First!)

The D flip-flop is useful when a single data bit (1 or 0) is to be stored. An additional inverter to the S-R flip-flop at the R input creates a D flip-flop. The D flip-flop shown below is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input.

If there is a HIGH on the D input when a clock pulse is applied, the flip-flop SETs and stores a 1. If there is a LOW on the D input when a clock pulse is applied, the flip-flop RESETs and stores a 0. The truth table below summarizes the operations of the positive edge-triggered D flip-flop. As before, the negative edge-triggered flip-flop works the same except that the falling edge of the clock pulse is the triggering edge.

(a) Logic diagram with NAND gates

(b) Graphical symbol

1 1 0 SET (stores 1)

0 0 1 RESET (stores a 0)

(c) Transition table

CP(CLK)

D (Input)

Q (Output)

(d) Waveform

Process for Standard, TTL and CMOS

D(elay) Flip-Flop (Standard)

The circuit of a D Type flip-flop has already been given to us. We are required to construct the given circuit using Design Architect ( DA). The constructed circuit is shown in figure 1 printed out using the lab printer.

Next, a symbol of the circuit is created using DA from the menu Miscellaneous followed by Generate Symbol. The created symbol is than modified. The modified symbol is shown in figure 2.

Next, Quicksim is activated mainly to invoke forces on the constructed circuit and to Trace as well as to analyze the output of the circuit through waveforms.

The saved file of the constructed circuit using DA is opened in Quicksim. Firstly, the function TRACE is used to trace PRE, CLR, CLK, D, Q, QB. After this a Trace box will appear at bottom lower left of the screen. This is where the simulated waveforms will apprear.

Forces is then added to each of the traced components except for Q and QB.

Component Value of Force

PRE 1 at time 0

CLR 0 at time 0 and 1 at time 35

CLK Period 100, 50% duty cycle

D Period 160, 50% duty cycle

After forcing the components with the required values, type RUN 800. The waveforms will appear exactly the same as the required waveforms printed out in figure 3. (please note that the traced components are included in the waveform results)

As we can see clearly in figure 3, the inputs of D are copied straight to the output Q. Transitions occurs at every positive-edge of the clock. Therefore the waveforms agree with the specification mentioned above.

Next, an experiment is done by changing the PRE and CLR to low. Theoretically, an illegal output would happen. The traced output with the above configuration is printed in figure 4. We can see that when both PRE and CLR are low resulting the output of Q and QB to be high. QB is defined to be the opposite of Q. However this happens ( both are High) due to the fact that both PRE and CLR are set to low. Therefore it is said that the output gives an illegal operation. This is because PRE and CLK cannot be set to low at the same time. PRE has to be HIGH to give an output.

The next operation done to the D flip-flop is to analyze the output when the CLK and input D changes simultaneously. We do this by adding force to the CLK and D by using the Stimulus in the menu and then clicking on ADD CLOCK(remember to delete the previous forces). We set the period of CLK to be 100 with 50% duty cycle and 150 is set for D. The output waveform is printed in figure 5.

By looking at the Q output waveform, we note that at every positive rising edge of CLK and D which in this case happens simultaneously gives an oscillated output. Why does this happen?

We have to first understand the basic concept of Timing factors. Below is a graphical explanation of the time behavior of cell.

CLK

Input

State

Time Behavior of Cell

? Setup time (tsu) is the minimum interval from the stabilization of the cell input to the triggering edge of the clock.

? Hold time (th) is the minimum time interval from the triggering edge of the clock to a subsequent change in the input to the cell.

? Propagation delay (tw) is the time interval from the triggering edge of the clock to the stabilization of the new state(cell output). When it is appropriate, we distinguish low-to-high and high-to-low propagation delays.

After reading through the time behavior of cell (taken from Introduction to Digital Systems by Milos Ercegovac, Tomas Lang and Jaime H.Moreno) we now can conclude that the oscillation happens due to the fact that the output cannot be determined whether to set to high or low. It is set in such a way that whenever CLK and D triggers to High simultaneously, oscillation occurs (figure 5). The lack of setup up time is the reason why oscillation happens.

TTL

The next section of the assignment takes a look at TTL delays. The standard D flip-flop file which was saved in the beginning is copied into a new file called dfilp_ttl. This is done by opening the previous dflip file and saving it, typing the path name as dflip_ttl.

Delays are inserted by clicking on change value in Design Architect. Select all the numbers beside the gates (initially 0) and then change the values. The upper number is the Rise time and the lower number is the Fall time. By default the values are in nanoseconds.

The values for the 2 gates are tabulated below.

Gate Rise Fall

NAND 17 15

BUF 20 6

In order for the delays to take effect on the circuit, we have to first activate the delays by clicking on SETUP, Analysis and then click on Delay. Trace all the components and type RUN 800. The output waveform is shown in figure 6.

It is seen here that with delay the output Q is shifted to the right. However, as marked on the waveform (A) as the CLK is triggered as D goes low, the output Q should go low. Due to the insufficient setup time for D, the output Q have no choice but to go high.

When the CLK and D occurs simultaneously, invalid operation occurs at the output. Q is not the exact complement of QB, shown in figure 7. Similar results are acquired as PRE and CLK goes low, shown in figure 8.

The minimum period for the circuit to work properly is found to be 34.1ns. Basically, whatever is lower than the minimum period which is also the maximum operating frequency(1/34ns = 29.41Mhz) , the circuit will not work correctly. The output would be invalid. How do we find the maximum operating frequency? 1 way is to go through Trial and Error. By reducing the period until we get an invalid output. As shown in figure 9 and figure 10 the period of CLK is reduced to 50 and 40 respectively. The output is still valid.

As we can see in figure 11, the output is invalid because Q is not completely the complement of QB This happens when the CLK period is set to 34ns.

Another explanation is through basic calculation. We know that the rise time and fall time delay for the NAND gates are 17 and 15 respectively. With the help of the diagrams below, we would have a better understanding.

CLK

Q

Minimum Operating Period

For the data to be copied to the output, the time taken for D to reach HIGH is 17ns and to reach LOW is 15ns. Adding both the time we get 33ns. Which means that the minimum period would be 34ns. Any period lower then that, output would be invalid.

CMOS

The circuit in TTL configuration is used. The previous forces of the NAND gates and buffer are replaced by values as shown below. The circuit is shown in figure 12.

Gate Rise Fall

NAND 160 160

BUF 80 40

The procedures are repeated as in simulating the standard D flip-flop in the beginning.

However, due to the fact that the Trace is initially in nanoseconds and therefore output waveform cannot be seen clearly, the environment is changed to microseconds.

The output waveform is shown in figure 13.

The CLK period is set to 100us.

When PRE and CLK are set to LOW, invalid output occurs. Result shown in figure 14

When the CLK and D of CMOS changes simultaneously, oscillation happens. Figure shown in figure 15.

The maximum operating frequency is found to be 1/0.33us = 3.03Mhz shown in figure 16

By completing the above assignment, it has given the user an in-depth understanding on the operation on standard TTL and CMOS. Both devices are basically constructed from the standard D-flip flop configuration.

By experimenting with the 3 different configured device, we can conclude that they have significant similarities and differences. One of which is that similar results occur when PRE and CLK are set to LOW. The output Q is not the exact complement of QB. Both Q and QB are HIGH. This is because that PRE has to be set to HIGH for an output.

Another similarity between standard and CMOS D Flip-Flop is that when CLK and D occurs simultaneously, the output at that point oscillates. This is explained in the above timing behavioral diagram. As for the TTL, output is invalid.

The most significant difference is the delay time. The delay for TTL is much shorter as compared to CMOS.

Time management is very essential in completing this assignment. This is because only a specific of time is allocated for each student to use the licensed Mentor Graphics. Furthermore, it gives students an in depth understanding of the operation, characteristics of the D Flip-Flop, TTL and CMOS and configurations.

It is essential to take this given opportunity to master the software as to assist us in completing 2nd assignment.

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